Microchip Technology SAMA5D2 Series 32-Bit Microprocessors

Microchip Technology SAMA5D2 Series 32-Bit Microprocessors are high-performance, ultra-low-power MPUs based on the Arm® Cortex®-A5 Core. The Cortex A5 Processor runs up to 500MHz and features the Arm Neon™ SIMD technology engine, a 128KB L2 cache, and a Floating Point Unit (FPU). It supports multiple memories, including DDR3, LPDDR3, and QSPI Flash. These devices integrate powerful peripherals for connectivity, including EMAC, USB, dual CAN, up to 10 UARTs, and more. The SAMA5D2 MPUs also offer a broad range of integrated user interface applications, such as TFT LCD controllers, projected capacitive and resistive touch controllers, class D amplifiers, audio PLL, and CMOS sensor interfaces.

The Microchip Technology SAMA5D2 MPUs offer advanced security functions to protect customer code and secure external data transfers. They include Arm TrustZone® technology, tamper detection, secure data storage, hardware encryption engine, on-the-fly decryption of code stored in external DDR or QSPI memory, and a secure bootloader.

Features

ARM Cortex-A5 core
- ARMv7-A architecture
- ARM TrustZone
- NEON Media Processing Engine
- Up to 500MHz
- ETM™/ETB™ 8 Kbytes
Memory Architecture
- Memory Management Unit
- 32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache
- 128-Kbyte L2 cache configurable to be used as an internal SRAM
- One 128-Kbyte scrambled internal SRAM
- One 160-Kbyte internal ROM
- 64-Kbyte scrambled and maskable ROM embedding Microchip boot loader/Microchip Secure boot loader
- 96-Kbyte unscrambled, unmaskable ROM for NAND Flash BCH ECC table
- High-bandwidth scrambled 16-bit or 32-bit Double Data Rate (DDR) multi-port dynamic RAM controller supporting up to 512Mbyte 8-bank DDR2/DDR3 (DLL off only)/DDR3L (DLL off only)/LPDDR1/LPDDR2/LPDDR3, including "on-the-fly" encryption/decryption path
- 8-bit SLC/MLC NAND controller, with up to 32-bit Error Correcting Code (PMECC)

Low-Power Modes
- Ultra Low-power mode with fast wake-up capability
- Low-power Backup mode with 5-Kbyte SRAM and SleepWalking features
  - Wake-up from up to nine wake-up pins, UART reception, analog comparison
  - Fast wake-up capability
  - Extended Backup mode with DDR in Self-Refresh mode
Up to 128 I/Os
- Fully programmable through set/clear registers
- Multiplexing of up to eight peripheral functions per I/O line
- Each I/O line can be assigned to a peripheral or used as a general purpose I/O
- The PIO controller features a synchronous output providing up to 32 bits of data output in one write operation
Packages
- 289-ball BGA, 14x14mm body, 0.8mm pitch
- 256-ball BGA, 8x8mm body, 0.4mm pitch
- 196-ball BGA, 11x11mm body, 0.75mm pitch