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Precision Analog Reference Voltage from Smaller, Low-cost Mixed Signal Devices

By Archana Yarlagadda, Applications Engineer, Cypress Semiconductor

Introduction

One of the main focuses in electronic devices is reduction of size, while keeping the same feature set. This reduction in size is considered at every step of the system, from transistor size to chip size and of the end product size. The shrinking in the size doesn’t always carry the same feature set. Sometimes certain properties, which are less commonly used, are removed to save the area. If these features are required, then the user is forced to use higher sized/priced chips that still have the features. Some innovative ideas are required to use the lower cost chips and achieve the required features, and this article focuses on one such feature in mixed signal devices. This feature is beneficial in devices with mixed signal capabilities and the term System on Chips (SoC) will be used in this article to refer to these devices.

Many applications using SoC convert analog signals into a digital signal and perform operations in the digital domain or in firmware. Thus there are many SoC devices in the market to target such applications that have limited analog capabilities, limited to a comparator and Analog to Digital Convertor (ADC). Since the end result is in the digital domain there is less requirement for analog output pins. As an analog output pin requires an analog bus and also analog buffers, to provide the external drive capability, a large amount of area can be saved my taking out these pins.

In certain applications, though all the signal processing is in the digital domain, an analog reference voltage is required. For example, consider a system with the ADC range of 0 to 5 V and the input signal value of ±20 mV. This input signal cannot be measured directly with the ADC. ADC offset has to be added to input signal, by using an external reference voltage, to shift it into the range of ADC. The offset can be compensated inside the firmware, after measurement. With the limited analog capability and no analog output pins, obtaining an output analog voltage reference is a challenge.

The focus of this article is to obtain the analog voltage reference feature, in the small sized chips with no analog output pins, with the use of a few external passive components.

Basic Method

Every system has a supply voltage that can be used directly as the reference voltage or indirectly to obtain another voltage reference. A resistive divider method is the basic form of obtaining a voltage reference from the supply voltage as shown in Figure 1A. This basic circuit has no control loop and has the disadvantage that the reference voltage is directly proportional to the supply voltage variations.


Figure 1: Reference voltage using resistor divider circuits

To regulate the voltage or to obtain different voltages, a control loop can be added to this circuit as shown in Figure 1B. The reference voltage can be measured and the resistance can be adjusted to maintain the required reference value. One end of the resistors is connected to the Vref node and the other end of the resistors is controlled through the pins. The pins can be either grounded or left at high Z. If the pin is grounded, the corresponding resistor is added into the effective resistance calculation, and if it is High Z, it is same as not connected. The reference voltage is obtained based on the effective resistance of resistors in parallel (Reff), as shown in equation below.

When a reference voltage is not required in the application, all the pins can be kept at high Z, thus saving power. The resolution of control can be increased by increasing the number of control resistors, which in turn increase the number of pins, to form a resistive chain control. The concept of resistive chain control can be used to regulate the reference voltage, or it can also be used to obtain different reference voltages at different times. To regulate the voltage, this type of control will work only when the variation is slower than the delay of the control.

Traditional PWM-DAC Method

The Pulse Width Modulator-Digital to Analog Convertor (PWM-DAC) is most widely used method to obtain a programmable reference voltage out of a digital pin. The output of PWM is a digital signal, which is low pass filtered to obtain the average DC value as shown in Figure 2. The cut-off frequency of the low pass filter should be chosen such that it is much lower than the frequency output of the PWM, to ensure as close to DC value as possible.


Figure 2: Pulse width modulation methods to generate constant reference voltage

The reference voltage, in this method, is a function of supply voltage (Vdd) and duty cycle (D) of the PWM as shown in equation below. If the supply voltage is 5 V, and the duty cycle is 50%, the reference voltage is 2.5V.

The pulse width can be varied to change Vref, but the PWM-DAC method is an open loop system and thus it is advantageous only when the supply voltage is highly accurate. If the supply voltage has error, then output reference voltage will also have error. Obtaining an accurate supply voltage is expensive and thus not available in low cost systems. To compensate for the change in supply voltage, a closed loop system can be formed by using an ADC and firmware control as shown in Figure 2B. The reference voltage value is measured using the ADC and the duty cycle of PWM is adjusted in the firmware to obtain the required reference value. This feedback loop will reduce the dependency on the supply voltage, but adds latency and uses more resources in the system.

Self Modulated Voltage Reference (Patent Pending*)

The earlier described methods were dependent on the supply voltage and had disadvantages based on the same. The self-modulated circuit is based on the assumption that though there are limited analog components, the SoC still has an internal reference voltage. This is often true in systems with an ADC. This method shows the technique to access this analog voltage externally on a digital pin. The PWM-DAC method was based on pulse width modulation and this new technique is based on the Pulse Density Modulation (PDM) principle, where, density of a digital signal is the percentage of time the signal is high.

The density of a signal is the percentage of ‘1’s in the digital signal stream of ‘1’s and ‘0’s. The particular waveform is not important, just the percentage that the signal is high is important. More information about the density signal processing is given in the references provided.

The circuit uses a synchronous comparator in SoC, and an external low pass filter as shown in Figure 3. The output of the low pass filter is the feedback, through an analog input pin, to the negative input of the comparator. The comparator with this feedback follows the same rules as an operational amplifier in voltage follower mode. The output of the voltage follower will change, as required, to keep its two inputs at the same level. If the value on the positive input is higher than the value on the negative input, the output is high. The high output will cause the output of the low pass filter to drift higher, eventually making the negative input to the comparator higher than the positive input. When the negative input is higher, the output remains low, which will pull the negative input lower. Thus the percentage of time that the signal is high, i.e. the density of the signal, changes to keep the two inputs at the same value. Eventually this will reach a stable state where it modulates its own output so that its density results in Vref = Vbg on the output of the low pass filter. Since the comparator is clocked, its output is a well-defined digital signal that is low-pass filtered to obtain a DC reference voltage.


Figure 3: Self modulated voltage reference circuit

Voltages other than the internal reference voltage (Vbg) can be obtained by adding an attenuator. If the attenuator is added on the output, then references less Vbg can be obtained. If an attenuator is added in the feedback, then references greater than Vbg can be obtained. This attenuation can be analog domain or in the density domain.

Density Attenuation

Since the principle of self-modulating circuit is based on PDM, additional circuits can be added for density modulation to obtain different embodiments of the main circuit. A density modulator (a PWM in this case) is added between the output of the comparator and the feedback signal, as shown in Figure 4A.


Figure 4. Embodiments of the self-modulator circuit
Amplifier

If the PWM output has a duty cycle of 50%, in Figure 4A, then the effective density at the output of the AND gate is half of what it was before. This will cause the negative input value to be low for double the time, and thus doubling the output density of the comparator. Thus, the density at the output of the comparator changes based on the duty cycle of the PWM. This digital density signal is low pass filtered to obtain a DC value, that depends on the internal bandgap reference voltage and the duty cycle of the PWM as shown in equation below.

Thus a programmable voltage reference by changing the PWM duty cycle is obtained, without the disadvantages of the PWM-DAC method. Since Dout2 cannot be less than zero, Vref2 cannot be less than Vbg.

Attenuator

The same components can be rearranged as shown in Figure 4B to achieve voltages less than the reference voltage, i.e. attenuator with the density modulation. In this method the output is given by the equation below.

Analog Attenuation

A resistor analog attenuator like a resistive divider circuit can be used to obtain attenuation in analog path and obtain voltages other than the reference voltage.

Amplifier

The self-modulated circuit can be used to obtain voltages higher (Amplifier) than the internal reference voltage by adding analog attenuator as shown in Figure 4C. The reference voltage value is shown in equation below

Attenuator

The self-modulated circuit can also be used to obtain voltages lower (Attenuator) than the internal reference voltage by adding external resistors as shown in Figure 4D. The reference voltage is obtained as shown in equation below

Buffer

The comparator in self-modulator configuration can be used as a buffer, when both inputs are available externally. The accuracy of the buffer will be same as the one explained for the reference voltage. The block diagram for the buffer mode will be the same as Figure 3, with the internal reference voltage Vbg replaced with an external input voltage.

Accuracy and dependency

The low pass filter used, to obtain a DC value from the digital signal, in the two methods determine the settling time and accuracy of the output signal. The pole of the low pass filter has to be chosen based on the frequency of the PWM in case of the PWM-DAC method and comparator clock frequency in the self-modulating method. If the pole of the low pass filter is too high, then Vout will not reach a study state value. Considering Fclk as the internal clock frequency, the requirement for the low pass filter is given in equation below:

The resistor chain and the PWM method are directly proportional to the supply voltage, whereas the variation of the self-modulated reference voltage depends on the variation of the bandgap voltage and offsets of the comparator. An implementation of the self-modulating circuit was built using Cypress Programmable System on Chip (PSoC) in order to collect performace data. The variation of the internal reference bandgap voltage and externally obtained reference voltage, across Vdd is given in Figure 5.


Figure 5. Variation of the reference voltage with supply voltage and temperature

The graph is plotted with data collected from the circuit implemented in the smallest PSoC chip CY8C21123. The average offset voltage of the comparator, in the device (CY8C21123) used for testing, is 8 mV. It is observed that the external voltage reference dependency on the supply voltage depends on the variation of the bandgap reference voltage and comparator parameters (offset) with supply voltage.

The temperature dependency of the first two methods is negligible. The self-modulating voltage reference circuit depends on the variation of the bandgap voltage and offset variation with temperature. The variation of reference voltage with temperature is shown in Figure 5. The temperature variation tracks the Vbg almost exactly. The comparator non-ideal parameters like offset vary differently with supply variation as compared to the temperature variation. This causes a higher deviation in output reference voltage from the internal reference voltage, with variation of Vdd.

The load drive capability of all the methods discussed is less than a buffered voltage output, since the effective resistance at the output is not zero. The drive capability is the least, among the three, in the first method. The resistance connected to this node has to be much higher than the effective resistance (Reff). The load drive capability of the PWM-DAC is same as any low pass filter.

The load drive capability of the self-modulating circuit is obtained by considering an ideal comparator. The feedback resistor (low pass filter resistor) (Rlp) determines the drive capacity of the circuit. Since the output changes to maintain the two inputs to the comparator at the same value, the constraint on the load resistance is given in equation below:

Conclusion:

This article shows methods of obtaining analog voltage reference values from chips that have limited analog capability. It can be used in systems that have analog capabilities already used for other purpose. A combination of the circuits can be used to obtain different voltage references. This provides more flexibility and programmability to obtain an analog voltage reference from a system that has limited analog capability.

*Disclaimer:

These design ideas have a Provisional patent and the actual patent is pending. Cypress has the rights for this circuit and the customers can use this circuit with Cypress parts.

The Cypress team (Archana Yarlagadda (yara@cypress.com), Dave Van Ess or Jeff Dahlin) has to be contacted if any of these circuits are to be used in any application.

Acknowledgments:

I thank Jeff Dahlin and Dave Van Ess for their ideas and guidance during the self-modulation circuit. I greatly appreciate Jeff’s review and suggestions to this article.

References:

Archana is an Applications Engineer in Cypress Semiconductors, working on the Programmable System on Chip (PSoC) application designs. She has her M.S.E.E in analog circuits from University of Tennessee, Knoxville. Her area of interest is mixed signal designs.